In wireless communication processing and the like, generally a multi-processor system that performs various processing in parallel using a plurality of cores is used. A bus is used for access, for example, between the respective cores and between the cores and a memory. In this bus access, when there is an access conflict between a plurality of masters for simultaneous access on a certain bus, an access arbiter for arbitrating the conflicting bus access is required.
In regard to an access arbiter related to the present invention, as an access arbitration method for realizing the access arbiter, the “round robin method” and “fixed priority method” have mainly been used. The “round robin method” is a method that does not take priorities into account in particular and sequentially provides each of the masters with an access privilege with an equal probability. The access arbiter is realized with a circuit configuration that has, for example, states for each of the connected masters and sees whether or not there is an access command in an ascending order.
Meanwhile, the “fixed priority method” is a method that provides the access privilege to the master having the highest priority when access commands conflict. The “fixed priority method” is characterized in that the circuit configuration is simple because the priorities are fixed and states are not included in particular. However, in the case of the “fixed priority method”, when there is a possibility that the master having a high priority performs sequential access, the other masters are not provided with the access privilege at all in a period while the master with the high access privilege performs sequential access. Therefore, there is a significant problem that the number of worst cycles cannot be estimated, and thus the performance cannot be guaranteed. Accordingly, generally the “round robin method” is used more often than the “fixed priority method”, however the “round robin method” has a problem that the priorities cannot be taken into account.
Further, in recent years, there is a high-speed on-chip bus interface capable of stream access. This bus interface standard supports split transfer (pipeline transfer) of an address and data at the time of reading in order to increase the speed of access. This bus interface standard is, for example, OCP (Open Core Protocol) or AXI (Advanced eXtensible Interface). By using such a bus interface standard that is capable of split transfer in which a request phase (address) and a response phase (data) are separated, it is possible to sequentially issue read addresses without depending on data latency at the time of reading. Accordingly, with an increase in the size of a system and an improvement of the speed of operating clock frequencies, even when the number of latency cycles at the time of reading increases, it is possible to perform stream access at a high transfer throughput by using a bus capable of split transfer.
Further, in recent years, with an increase in the size of the system, a bus configuration often used is a hierarchical bus configuration in which a bus is divided into several sections, a plurality of bus interfaces are combined, and connections are made in stages.
As a technique related to the present invention, there is, for example, a technique disclosed in Patent Literature 1. Patent Literature 1 suggests a bus system technique for coupling a plurality of masters to a bus based on the Open Core Protocol (OCP). In addition to a bus arbiter circuit for arbitrating access from a plurality of masters, this bus system technique further includes an FIFO buffer circuit for sequentially storing access master information at the time of reading so as to enable the split transfer, which is a feature of the OCP. In this way, even with a bus capable of split transfer, read data can be returned to a desired master using the master information stored to FIFO at the time of returning the read data to the master. Thus, this bus system technique has a benefit that it is capable of performing sequential transfer while arbitrating read access from a plurality of masters.
As another technique related to the present invention, there is a technique disclosed in Patent Literature 2. Patent Literature 2 suggests a bus control technique when the bus interface standard capable of split transfer is used as a hierarchical bus. This bus control technique performs, in parallel to cache snoop processing of a preceding stage, access arbitration processing of a subsequent stage early at the time of accessing the hierarchical bus in the preceding stage and the subsequent stage, to thereby realize an improvement of the speed of bus access.
However, as mentioned in Patent Literature 3, which is another related technique, in a bus interface capable of split transfer, there is a problem that when latency (the number of return cycles) of read data differs according to an access destination (slave), bus access to different access destinations (slaves) cannot be sequentially transferred eventually.
In particular, in the hierarchical bus configuration using the bus interface capable of split transfer, when the access arbitration is performed by the “round-robin method” that provides access privileges to a plurality of masters in the preceding stage with an equal probability, for example, when a master A issues read access to a slave 1 and a master B issues read access to a slave 2 sequentially, the masters A and B are provided with access privileges alternately according to the round robin method, and on the bus of the subsequent bus, there will be alternate read access to different slaves, which are the slaves 1 and 2.
In this case, there is a problem that, in order to prevent conflict of read data on the bus of the subsequent stage and Out-Of-Order transfer, the read access to different access destinations (slaves) cannot be transferred sequentially, and Wait is generated in each access, thereby deteriorating the transfer throughput. However, in the case where the bus interface standard supports “burst transfer”, and further, each of the masters can explicitly specify “burst” using a dedicated signal, if the access arbitration is performed per “burst transfer” on the bus of the preceding stage, constant and sequential access is ensured in the subsequent stage, thereby preventing deterioration of the transfer throughput.
However, in wireless communication processing that uses the multi-processor system of the present invention, sequential access, in which a master side cannot explicitly specify burst (addresses are non-sequential) such as interleave processing for rearranging data, frequently occurs. Therefore, there is a problem that the “burst transfer” cannot be used. Further, when the bus interface supports the “burst transfer”, there is a problem that the circuit configuration associated with the bus becomes complicated.
Moreover, as another related technique for solving the above-mentioned problems, there is a technique disclosed in Patent Literature 4. Patent Literature 4 suggests a technique for limiting the number of sequential execution in a transfer phase for a plurality of access requests to N. This technique is to limit, for example, the number of sequential execution of a master having a high priority, and provide an access privilege to a master having a low priority with a constant probability, so as to guarantee the number of access cycles in a worst case and equalize access performance of the masters as much as possible.
However, this access arbitration method is effective when each master often performs sequential access, like in a cache, however when single access and sequential access is mixed according to the processing, it is necessary to keep the master wait for a predetermined period to determine whether or not the state of the master is the sequential access, even if the states of the masters are the single access. Therefore, there is a problem that the access performance deteriorates more than in a common round robin method.
Note that as another technique related to the present invention, there are techniques disclosed in Patent Literatures 5 to 7. However, Patent Literature 5 only discloses a method for “judging whether or not to continue sequential access based on a judgment result in the case of round robin arbitration” and does not disclose a configuration of “dynamically performing an access mode judgment in advance and dynamically switching an access arbitration mode for each master whether or not to perform round robin arbitration based on the judgment result”.
Further, there is a problem in the technique disclosed in Patent Literature 5 that it requires a signal for access arbitration to be output for each access from the master side, thereby generating an overhead. Another problem is that, in a manner similar to the above-mentioned Patent Literature 4, when single access for control and sequential access for data processing is generated at a certain frequency from each master core, access arbitration cannot be carried out efficiently (because the access mode judgment is not performed in advance).
Patent Literature 6 discloses a method of “switching between a determining mode that has a bus ownership for a fixed period of time and an adaptive mode capable of round robin allocation”. However, in Patent Literature 6, it is necessary to “statically set the mode from outside using a mode setting parameter”, and it is not possible to “dynamically switch the access mode itself based on the judgment result”.
Furthermore, there is a problem in the technique disclosed in Patent Literature 6 that there is an overhead in which mode setting is required as appropriate. Moreover, at the time of actual usage, when single access for control and sequential access for data processing is generated at a certain frequency from each master core or when each master core is multi-tasking, there is a problem that it is difficult to set the mode efficiently in advance.
Additionally, in a manner similar to Patent Literature 5, Patent Literature 7 does not to disclose a configuration of “judging an access mode in advance and dynamically switching the access mode afterward”.